By Barbara Chapman, Weimin Zheng, Guang R. Gao, Mitsuhisa Sato, Eduard Ayguadé, Dongsheng Wang
This publication constitutes the completely refereed post-workshop lawsuits of the 3rd foreign Workshop on OpenMP, IWOMP 2007, held in Beijing, China, in June 2007.
The 14 revised complete papers and eight revised brief papers provided have been conscientiously reviewed and chosen from 28 submissions. The papers handle all themes regarding OpenMP, akin to OpenMP functionality research and modeling, OpenMP functionality and correctness instruments and proposed OpenMP extensions, in addition to purposes in numerous domain names, e.g., clinical computation, games, special effects, multimedia, info retrieval, optimization, textual content processing, facts mining, finance, sign and picture processing, and numerical solvers.
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Additional resources for A Practical Programming Model for the Multi-Core Era: 3rd International Workshop on OpenMP, IWOMP 2007, Beijing, China, June 3-7, 2007 Proceedings
Milovanovi´c et al.
5) is lower than the density (1) of the programs in Figure 4. In other words, the program has better inherent concurrency and can therefore be parallelised more efficiently. This demonstrates the general scalability of our approach. Second, while the performance of the programs decreases with the increase of the density, there is one exception. 5). The reason lies in the dependence structure of the programs. 95 is a highly regular program with two layers of nodes in the task graph. Nodes in the same layer are independent of each other, which implies a high inherent concurrency, hence it enables better scalability.
Again, to test the performance impact of workload ordering, we use “zone_sort_id” to store the sorted zone ids. 4 Performance Results In this section, we present performance results obtained on a large shared memory system. We will ﬁrst give a brief description of the system and programming support. 1 Testing Environment For our study, we used an SGI Altix 3700BX2 system that is one of the 20 nodes in the Columbia supercomputer installed at NASA Ames Research Center . 6 GHz and containing 9 MB on-chip L3 data cache.